The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to a method of placing datapath cells within a datapath macro to minimize signal propagation time and datapath macro area.
Integrated circuits typically include datapath macros. A datapath macro is an arrangement of datapath blocks connected by data buses and control signals. The data buses are generally routed orthogonally to the control signals. Each datapath block contains one or more datapath cells. Each of the datapath cells are connected to one or more of the data buses and to one or more of the control signals. As the size and complexity of the datapath macros and constituent datapath blocks increases, it becomes increasingly difficult for cell placement tools to arrange the datapath cells so that the signal propagation time through the datapath macro and the area of the datapath macro are minimized under complex input constraints imposed on the placement of cells, pins, nets, gaps between cells, and so on. As the size and complexity of the datapath macros and constituent datapath blocks increases, therefore, signal propagation time through the datapath macro and the area of the datapath macro may be not be optimally minimized.
The present invention advantageously addresses the problems above as well as other problems by providing a method of datapath cell placement that minimizes signal propagation time and datapath macro area.
In one embodiment, the present invention may be characterized as a method of datapath cell placement that includes the steps of receiving as input a datapath description for a datapath block wherein the datapath description describes at least one of a plurality of datapath cells, a plurality of data input pins, a plurality of data output pins, and a plurality of control signal pins; sorting the plurality of data input pins and the plurality of data output pins according to a hierarchy of constraint criteria; determining a plurality of corresponding criticality values for the plurality of datapath cells; sorting the plurality of datapath cells according to the plurality of corresponding criticality values; assigning the plurality of datapath cells to a plurality of corresponding columns; and arranging the plurality of datapath cells within at least one of the plurality of corresponding columns to minimize signal propagation delay through the datapath block.